Version	New instructions	New features
ARMv1	AND, EOR, SUB, RSB, ADD, ADC, SBC, RSC TST, TEQ, CMP, CMN, ORR, MOV, BIC, MVN STR, LDR, STM, LDM, B, BL, SWI	25 registers usr, fiq, irq, svc modes
ARMv2	MUL, MLA STC, LDC, CDO (CDP), MRC, MCR	Coprocessors R8_fiq, R9_fiq
ARMv2a	SWP, SWPB	Coprocessor 15 as control
ARMv3	MRS, MSR	32-bit modes abt, und modes R13_abt, R14_abt, R13_und, R14_und CPSR, SPSR_fiq, SPSR_irq, SPSR_svc, SPSR_abt, SPSR_und
ARMv3M	UMULL, UMLAL, SMULL, SMLAL
ARMv4	STRH, LDRH, LDRSB, LDRSH	sys mode
ARMv4T	BX	Thumb version 1 (THUMBv1)
ARMv5T	CLZ, BKPT, BLX Rm BLX imm, STC2, LDC2, CDP2, MRC2, MCR2	Thumb version 2 (THUMBv2) VFP coprocessor extension (VFPv1D/VFPv1xD; coprocessors 10, 11)
ARMv5TExP	QADD, QDADD, QSUB, QDSUB SMULxy, SMULWy, SMLAxy, SMLALxy, SMLAWy
ARMv5TE	STRD, LDRD, MCRR, MRRC, PLD	VFPv2
ARMv5TEJ	BXJ …	Jazelle architecture extension …
ARMv6	CPS, SRS, RFE REV, REV16, REVSH SETEND LDREX, STREX SXTB, SXTH, UXTB, UXTH (SIMD) (64-bit multiply-accumulate) CPY …	Thumb version 3 (THUMBv3) Debug architecture (coprocessor 14) Unaligned access support …
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