| Coprocessor instruction |
Treated as undefined (regardless of condition field). |
| Comparison instruction without S bit |
No-op. |
| Data processing register shift, bit 7 set |
Treated as if bit 7 clear. |
| Load/store “register shift” (bit 4 set, bit 7 clear) |
Loads as a register shift, but any writeback as if immediate shift, taking an extra cycle overall. Stores as if bit 4 clear, but still taking an extra cycle. |
| Load/store “register shift” (bit 4 set, bit 7 set) |
As above (bit 7 forming part of the immediate, but not Rs). |
LDM or STM with empty register list |
No load or store takes place (2 cycles for LDM, 1 cycle for STM), but if writeback, will be as if all registers (R0-R15) specified. LDM seems to cause a reset. |
LDR with Rd=Rn, pre-indexed |
Loaded value wins. |
LDR with Rd=Rn, post-indexed |
Loaded value wins. |
STR with Rd=Rn, pre-indexed |
Stores old value. |
STR with Rd=Rn, post-indexed |
Stores old value. |
Unaligned LDR |
Loads rotated value. |
Unaligned STR |
Effectively aligns address for purposes of the store (bottom 2 bits ignored), writeback value not affected though. |
Unaligned LDM |
Effectively aligns address for purposes of the loads (bottom 2 bits ignored), writeback value not affected though. |
Unaligned STM |
Effectively aligns address for purposes of the stores (bottom 2 bits ignored), writeback value not affected though. |
Load/store multiple with R15 base |
Uses current instruction + 2 (+8 bytes). |
| Modifying current instruction + 1 |
Old instruction executed. |
| Modifying current instruction + 2 |
Old instruction executed. |
| Modifying current instruction + 3 |
New instruction executed. |
| Executing @ 0x03fffffc |
Wraps around to 0 after. |
| Branching back past 0 or forward past 0x03fffffc |
Wraps around. Consequently, branch offset may be considered to be either signed or unsigned. |
BL @ 0x03fffff8 |
R14 has wrong PSR (1<<26 subtracted). |
SWI @ 0x03fffff8 |
R14_svc has wrong PSR (1<<26 subtracted). |
| Load/store multiple + address exception |
Only the first (lowest) transfer address is checked. Will wrap around to 0 subsequently. |